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this is information on a product in full production. october 2015 docid025449 rev 7 1/35 m24c64s-fcu 64-kbit serial i2c bus eeprom 4 balls csp datasheet - production data features ? compatible with the 400 khz i2c protocol ? high speed 1mhz transfer rate ? memory array: ? 64 kbit (8 kbyte) of eeprom ? page size: 32 byte ? supply voltage range: ? 1.7 v to 5.5 v ? operating temperature range ?v cc = 1.7 v to 5.5v over -40c / +85c ?v cc = 1.6 v to 5.5v over 0c / +85c ? write ? byte write within 5 ms ? page write within 5 ms ? random and sequential read modes ? software write protect ? upper quarter memory array ? upper half memory array ? upper 3/4 memory array ? whole memory array ? esd protection ? human body model: 4 kv ? more than 4 million write cycles ? more than 200-years data retention ? package ? wlcsp, rohs and halogen free compliant (ecopack2 ? ) wlcsp (cu) www.st.com
contents m24c64s-fcu 2/35 docid025449 rev 7 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 v ss (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4.1 operating supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4.3 device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4.4 power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.3 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.4 acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.5 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.2 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.3 write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.4 minimizing write delays by polling on ack . . . . . . . . . . . . . . . . . . . . . . 17 5.2 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.1 random address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.2 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.3 sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.4 read the write protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
docid025449 rev 7 3/35 m24c64s-fcu contents 3 7 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.1 ultra thin wlcsp package information . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
list of tables m24c64s-fcu 4/35 docid025449 rev 7 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5. write protect register (address = 1xxx.xxxx.xxxx.xxxxb) . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 9. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10. 400 khz ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 11. 1 mhz ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 12. ultra thin wlcsp- 4-bump, 0.833 x 0.833 mm, wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 13. ultra thin wlcsp- 4-bump, 0.833 x 0.833 mm, wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 14. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 15. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
docid025449 rev 7 5/35 m24c64s-fcu list of figures 5 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. 4-bump wlcsp connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. i 2 c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. write mode sequence (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6. write mode sequence (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. write cycle polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 figure 8. read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 400 khz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 10. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at 1 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 11. ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 12. ultra thin wlcsp- 4-bump, 0.833 x 0.833 mm, wafer level chip scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 13. ultra thin wlcsp- 4-bump, 0.833 x 0.833 mm, wafer level chip scale package outline with bsc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 14. thin wlcsp- 4-bump, 0.833 x 0.833 mm, wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
description m24c64s-fcu 6/35 docid025449 rev 7 1 description the m24c64s-fcu is a 64-kbit i2c-compatible eeprom (electrically erasable programmable memory) organized as 8 k 8 bits the m24c64s-fcu can operate with a supply voltage from 1.7 v to 5.5 v, over an ambient temperature range of -40 c/+85 c and with an extended supply voltage from 1.6 v to 5.5 v, over a reduced ambient temperature range. the m24c64s-fcu is delivered in a 4-ball wlcsp package. figure 1. logic diagram figure 2. 4-bump wlcsp connections (top view, marking side, with balls on the underside) table 1. signal names signal name function direction sda serial data i/o scl serial clock input v cc supply voltage - v ss ground - 069 9 && 9 66 6'$ 6&/ 0&6)&8 06y9 0dunlqjvlgh wrsylhz %xpsvlgh erwwrpylhz 9 && 9 66 6&/ 6'$ 9 && 9 66 6&/ 6'$ $ $ % %
docid025449 rev 7 7/35 m24c64s-fcu signal description 34 2 signal description 2.1 serial clock (scl) scl is an input. the signal applied on the scl input is used to strobe the data available on sda(in) and to output the data on sda(out). 2.2 serial data (sda) sda is an input/output used to transfer data in or data out of the device. sda(out) is an open drain output that may be wire-or?ed with other open drain or open collector signals on the bus. a pull-up resistor must be co nnected from serial data (sda) to v cc ( figure 9 indicates how to calculate the value of the pull-up resistor). 2.3 v ss (ground) v ss is the reference for the v cc supply voltage. 2.4 supply voltage (v cc ) 2.4.1 operating supply voltage (v cc ) prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see operating conditions in section 8: dc and ac parameters ) . in order to secure a stab le dc supply voltage, it is recommended to decouple the v cc line with a suitable ca pacitor (usually from10 nf to 100 nf) close to the v cc /v ss package pins. this voltage must remain stable and valid unt il the end of the transmission of the instruction and, for a write instructio n, until the completion of the internal write cycle (t w ). 2.4.2 power-up conditions the v cc voltage has to rise continuously from 0 v up to the minimum v cc operating voltage (see operating conditions in section 8: dc and ac parameters ) and the rise time must not vary faster than 1 v/s. 2.4.3 device reset in order to prevent inadvertent write operations during power-up, a power-on-reset (por) circuit is included. at power-up, the device does not re spond to any instruction until v cc has reached the internal reset threshold voltage. this threshold is lower than the minimum v cc operating voltage (see operating conditions in section 8: dc and ac parameters ). when v cc passes over the por threshold, the device is reset and enters the standby power mode; however, the device must not be accessed until v cc reaches a valid and stable dc voltage within the specified [v cc (min), v cc (max)] range (see operating conditions in section 8: dc and ac parameters ).
signal description m24c64s-fcu 8/35 docid025449 rev 7 in a similar way, during power-down (continuous decrease in v cc ), the device must not be accessed when v cc drops below v cc (min). when v cc drops below the power-on-reset threshold voltage, the device stops resp onding to any instruction sent to it. 2.4.4 power-down conditions during power-down (continuous decrease in v cc ), the device must be in the standby power mode (mode reached after decoding a stop condition, assuming that there is no internal write cycle in progress).
docid025449 rev 7 9/35 m24c64s-fcu memory organization 34 3 memory organization the memory is organized as shown below. figure 3. block diagram -36 #ontrollogic (ighvoltage generator )/shiftregister !ddressregister andcounter $ata register page 8decoder 9decoder 3#, 3$!
device operation m24c64s-fcu 10/35 docid025449 rev 7 4 device operation the device supports the i 2 c protocol. this is summarized in figure 4 . any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. the device that controls the data transfer is known as the bus master, and the other as the slave device. a dat a transfer can only be initia ted by the bus master, which will also provide the serial clock for synchronization. the device is always a slave in all communications. figure 4. i 2 c bus protocol 6&/ 6'$ 6&/ 6'$ 6'$ 67$57 &rqglwlrq 6'$ ,qsxw 6'$ &kdqjh $,' 6723 &rqglwlrq 06% $&. 67$57 &rqglwlrq 6&/ 06% $&. 6723 &rqglwlrq
docid025449 rev 7 11/35 m24c64s-fcu device operation 34 4.1 start condition start is identified by a falling edge of serial da ta (sda) while serial clock (scl) is stable in the high state. a start condition must prece de any data transfer instruction. the device continuously monitors (except during a writ e cycle) serial data (sda) and serial clock (scl) for a start condition. 4.2 stop condition stop is identified by a rising edge of serial da ta (sda) while serial clock (scl) is stable and driven high. a stop condition terminates communication between the device and the bus master. a read instruction that is followed by noack can be fo llowed by a stop condition to force the device into the standby mode. a stop condition at the end of a write instruction triggers the internal write cycle. 4.3 data input during data input, the device samples serial da ta (sda) on the rising edge of serial clock (scl). for correct device operation, serial data (sda) must be stable during the rising edge of serial clock (scl), and the serial data (sda) signal must change only when serial clock (scl) is driven low. 4.4 acknowledge bit (ack) the acknowledge bit is used to indicate a succ essful byte transfer. the bus transmitter, whether it be bus master or slave device, releas es serial data (sda) after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls serial data (sda) low to acknowledge the receipt of the eight data bits.
device operation m24c64s-fcu 12/35 docid025449 rev 7 4.5 device addressing to start communication between the bus master and the slave device, the bus master must initiate a start conditio n. following this, the bus master s ends the device select code, shown in table 2 (on serial data (sda), most significant bit first). the 8 th bit is the read/ write bit (r w ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the 9 th bit time. if the device does not match the device select co de, the device deselects itself from the bus, and goes into standby mode (therefore will not acknowle dge the device select code). table 2. device select code device type identifier (1) 1. the most significant bit, b7, is sent first. chip enable address rw b7 b6 b5 b4 b3 b2 b1 b0 1010001rw
docid025449 rev 7 13/35 m24c64s-fcu instructions 34 5 instructions 5.1 write operations following a start condition the bus master sends a device select code with the r/ w bit (r w ) reset to 0. the device acknowledges this, as shown in figure 5 , and waits for two address bytes. the device responds to each address byte with an acknowledge bit, and then waits for the data byte. when the bus master generates a stop condit ion immediately after a data byte ack bit (in the ?10 th bit? time slot), either at the end of a byte write or a page write, the internal write cycle t w is triggered. a stop condition at any othe r time slot does not trigger the internal write cycle. after the stop condition and the successful completion of an internal write cycle (t w ), the device internal address counter is automatically incremented to point to the next byte after the last modified byte. during the internal write cycle, serial data (s da) is disabled internally, and the device does not respond to any requests. table 3. most significant address byte a15 a14 a13 a12 a11 a10 a9 a8 table 4. least significant address byte a7 a6 a5 a4 a3 a2 a1 a0
instructions m24c64s-fcu 14/35 docid025449 rev 7 5.1.1 byte write after the device select code and the address byte s, the bus master send s one data byte. if the addressed location is write-protected, the device replies with noack, and the location is not modified, as shown in figure 6 . if, instead, the addressed location is not write- protected, the device replies with ack, as shown in figure 5 . the bus master shall terminate the transfer by generating a stop condition. figure 5. write mode sequence (data write enabled) 3top 3tart "yte7rite $evsel "yteaddr "yteaddr $atain 3tart 0age7rite $evsel "yteaddr "yteaddr $atain $atain !)e 0age7ritecontgd 3top $atain. !#+ 27 !#+ !#+ !#+ !#+ !#+ !#+ !#+ 27 !#+ !#+
docid025449 rev 7 15/35 m24c64s-fcu instructions 34 5.1.2 page write the page write mode allows up to 32 bytes to be written in a single write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, a15/ a5, are the same. if more bytes ar e sent than will fit up to the end of the page, a ?roll-over? occurs, i.e. the by tes exceeding the page end are written on the same page, from location 0. the bus master sends from 1 to 32 bytes of data, each of which is acknowledged by the device if the page is not write-protected, as shown in figure 5 . if the page is write-protected, the contents of the addressed memory location are not modified, and each data byte is followed by a noack, as shown in figure 6 . after each transferred byte, the internal page address counter is incremented. the transfer is terminated by the bu s master generating a stop condition. figure 6. write mode sequence (data write inhibited) stop start byte write dev sel byte addr byte addr data in start page write dev sel byte addr byte addr data in 1 data in 2 ai01120e page write (cont'd) stop data in n ack ack ack no ack r/w ack ack ack no ack r/w no ack no ack
instructions m24c64s-fcu 16/35 docid025449 rev 7 5.1.3 write protection by writing specific values in a register ( table 5 ) located at address 1xxx.xxxx.xxxx.xxxxb, the memory array can be write-protected by blocks, which size can be defined as: ? the upper quarter memory array ? the upper half memory array ? the upper 3/4 memory array ? the whole memory array note: location 1xxx.xxxx.xxxx.xxxxb is outside of the addressing field of the eeprom memory (16 kbytes are addressed within the 00xx.xxxx.xxxx.xxxx range) ? bit b3 enables or disables the write protection ? b3=0: the whole memory can be written (no write protection) ? b3=1: the concerned bl ock is write-protected ? bits b2 and b1 define the size of the me mory block to be protected against write instructions ? b2,b1=0,0: the upper quarter of memory is write-protected ? b2,b1=0,1: the upper half memory is write-protected ? b2,b1=1,0: the upper 3/4 of memory are write-protected ? b2,b1=1,1: the whole memory is write-protected ? bit b0 locks the write protect status ? b0=0: bits b3,b2, b1,b0 can be modified ? b0=1: bits b3,b2,b1,b0 cannot be modi fied and therefore the memory write protection is frozen. ? b7, b6, b5, b4 bits are don't care bits. writing the write protect register writing in the write protect register is perfo rmed with a byte write instruction at address 1xxx.xxxx.xxxx.xxxxb. bits b7,b6,b5,b4 of the da ta byte are not significant (don't care). writing more than one byte will discard the wr ite cycle (write protect register content will not be changed). table 5. write protect register (address = 1xxx.xxxx.xxxx.xxxxb) b7 b6 b5 b4 b3 b2 b1 b0 write x x x x write protect activation size of write protected block size of write protected block write protect lock read0000
docid025449 rev 7 17/35 m24c64s-fcu instructions 34 5.1.4 minimizing write delays by polling on ack during the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its intern al latches to the memory ce lls. the maximum write time (t w ) is shown in ac characteristics tables in section 8: dc and ac parameters , but the typical time is shorter. to make use of this, a pollin g sequence can be used by the bus master. the sequence, as shown in figure 7 , is: ? initial condition: a write cycle is in progress. ? step 1: the bus master issues a start condi tion followed by a device select code (the first byte of the new instruction). ? step 2: if the device is bu sy with the internal write cycl e, no ack will be returned and the bus master goes back to step 1. if t he device has terminated the internal write cycle, it responds with an ack, indicating th at the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). figure 7. write cycle polling flowchart using ack 1. the seven most significant bits of the device se lect code of a random read (bottom right box in the figure) must be identical to the seven most significant bi ts of the device select code of the write (polling instruction in the figure). :ulwhf\foh lqsurjuhvv $,h 1h[w 2shudwlrqlv dgguhvvlqjwkh phpru\ 6wduwfrqglwlrq $&. uhwxuqhg <(6 12 <(6 12 5h6wduw 6wrs 'dwdiruwkh :ulwhrshudwlrq 6hqg$gguhvv dqg5hfhlyh$&. <(6 12 &rqwlqxhwkh :ulwhrshudwlrq &rqwlqxhwkh 5dqgrp5hdgrshudwlrq 'hylfhvhohfw zlwk5: )luvwe\whrilqvwuxfwlrq zlwk5: douhdg\ ghfrghge\wkhghylfh 'hylfhvhohfw zlwk5: 6wduw&rqglwlrq
instructions m24c64s-fcu 18/35 docid025449 rev 7 5.2 read operations read operations are performed indepen dently of the write protection state. after the successful completion of a read oper ation, the device internal address counter is incremented by one, to point to the next byte address. for the read instructions, after each byte read (data out), the device waits for an acknowledgment (data in) during the 9th bit time. if the bus master does not acknowledge during this 9th time, the device terminates t he data transfer and switches to its standby mode. figure 8. read mode sequences 5.2.1 random address read a dummy write is first performed to load the address into this address counter (as shown in figure 8 ) but without sending a stop condition. then, the bus master sends another start condition, and repeats the device select code, with the r w bit set to 1. the device acknowledges this, and outputs the contents of the addressed byte. the bus master must not acknowledge the byte, and terminates the transfer with a stop condition. 3tart $evsel
"yteaddr "yteaddr 3tart $evsel $ataout !)d $ataout. 3top 3tart #urrent !ddress 2ead $evsel $ataout 2andom !ddress 2ead 3top 3tart $evsel
$ataout 3equential #urrent 2ead 3top $ataout. 3tart $evsel
"yteaddr "yteaddr 3equention 2andom 2ead 3tart $evsel
$ataout 3top !#+ 27 ./!#+ !#+ 27 !#+ !#+ !#+ 27 !#+ !#+ !#+ ./!#+ 27 ./!#+ !#+ !#+ !#+ 27 !#+ !#+ 27 !#+ ./!#+
docid025449 rev 7 19/35 m24c64s-fcu instructions 34 5.2.2 current address read for the current address read operation, following a start condition, the bus master only sends a device select code with the r/ w bit set to 1. the device acknowledges this, and outputs the byte addressed by the inter nal address counter. the counter is then incremented. the bus master terminates the transfer with a stop condition , as shown in figure 8 , without acknowledging the byte. 5.2.3 sequential read this operation can be used after a current address read or a random address read. the bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next by te in sequence. to terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 8 . the output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte ou tput. after the last memory address, the address counter ?rolls-over?, and the device continues to output data from memory address 00h. 5.2.4 read the write protect register reading the write protect register is performe d with a random read instruction at address 1xxx.xxxx.xxxx.xxxxb. bits b7, b6, b5, b4 of th e write protect register content are read as 0, 0, 0, 0. the signification of the protect re gister lower bits b3, b2, b1, b0 are defined in section 5.1.3: write protection . reading more than one byte will loop on reading the writ e protect register value. the write protect register cannot be read while a write cycle (t w ) is ongoing.
initial delivery state m24c64s-fcu 20/35 docid025449 rev 7 6 initial delivery state the device is delivered with all the memory array bits set to 1 (each byte contains ffh) and the write protect register set to 0 (00h).
docid025449 rev 7 21/35 m24c64s-fcu maximum rating 34 7 maximum rating stressing the device outside the ratings listed in table 6 may cause permanent damage to the device. these are stress ratings only, and o peration of the device at these, or any other conditions outside those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 6. absolute maximum ratings symbol parameter min. max. unit - ambient operating temperature ?40 130 c t stg storage temperature ?65 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec standard j-std-020d (for small-body, sn-pb or pb free assembly), the st ecopack? 7191395 specification, and the european dire ctive on restrictions on hazardous substances (rohs directive 2011/65/eu of july 2011). c v io input or output range ?0.50 6 v i ol dc output current (sda = 0) - 5 ma v cc supply voltage ?0.50 6 v v esd electrostatic pulse (human body model) - 4000 v
dc and ac parameters m24c64s-fcu 22/35 docid025449 rev 7 8 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. table 7. test conditions symbol parameter min. unit data retention (1) 1. the data retention behavior is checked in production. the 200-year limit is def ined from characterization and qualification results. ta = 55 c 200 year cycling ta = 25 c 4 million cycle table 8. operating conditions symbol parameter min. max. unit v cc supply voltage 1.60 1.70 5.5 v t a ambient operating temp erature: read ?40 ?40 85 c ambient operating temp erature: write 0 ?40 f c operating clock frequency, v cc = 1.6 v - 400 khz operating clock frequency, v cc = 1.7 v - 1000
docid025449 rev 7 23/35 m24c64s-fcu dc and ac parameters 34 table 9. dc characteristics symbol parameter test conditions min. max. unit i li input leakage current (scl, sda) v in = v ss or v cc device in standby mode - 2a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc - 2a i cc supply current (read) v cc < 1.8 v, f c = 400 khz - 0.8 ma v cc >= 1.8 v, f c = 400 khz - 2 ma v cc >= 1.8 v, f c = 1 mhz (1) 1. only for devices operating at f cmax = 1 mhz (see table 8 ) -2.5ma i cc0 supply current (write) (2) 2. characterized value, not tested in production. during t w -2ma i cc1 standby supply current device not selected (3) , v in = v ss or v cc , v cc = 1.8 v 3. the device is not selected after power-up, after a r ead instruction (after the stop condition), or after the completion of the internal write cycle t w (t w is triggered by the correct decoding of a write instruction). -1a device not selected (3) , v in = v ss or v cc , v cc = 2.5 v -2a device not selected (3) , v in = v ss or v cc , v cc = 5.5 v -3a v il input low voltage (scl, sda) - ?0.45 0.25 v cc v v ih input high voltage (scl, sda) -0.75 v cc v cc + 1 v v ol output low voltage i ol = 1 ma, v cc < 1.8 v - 0.2 v i ol = 2.1 ma, v cc = 2.5 v - 0.4 v i ol = 3 ma, v cc = 5.5 v - 0.4 v
dc and ac parameters m24c64s-fcu 24/35 docid025449 rev 7 table 10. 400 khz ac characteristics symbol alt. parameter min. max. unit f c f scl clock frequency - 400 khz t chcl t high clock pulse width high 600 - ns t clch t low clock pulse width low 1300 - ns t ql1ql2 (1) 1. characterized only, not tested in production. t f sda (out) fall time 20 (2) 2. with c l = 10 pf. 300 ns t xh1xh2 t r input signal rise time (3) 3. there is no min. or max. value for the input signal rise and fall times. it is however recommended by the i2c specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when f c < 400 khz. (3) ns t xl1xl2 t f input signal fall time (3) (3) ns t dxch t su:dat data in set up time 100 - ns t cldx t hd:dat data in hold time 0 - ns t clqx (4) 4. the min value for t clqx (data out hold time) offers a safe timing to bridge the undefined region of the falling edge scl. t dh data out hold time 50 - ns t clqv (5) 5. t clqv is the time (from the falling edge of scl) r equired by the sda bus line to reach either 0.3v cc or 0.7v cc , assuming that r bus c bus time constant is less than 400 ns . t aa clock low to next data valid (access time) - 900 ns t chdl t su:sta start condition setup time 600 - ns t dlcl t hd:sta start condition hold time 600 - ns t chdh t su:sto stop condition set up time 600 - ns t dhdl t buf time between stop condition and next start condition 1300 - ns t w t wr write time - 5 ms t ns (1) - pulse width ignored (input filter on scl and sda) - single glitch -50ns
docid025449 rev 7 25/35 m24c64s-fcu dc and ac parameters 34 table 11. 1 mhz ac characteristics symbol alt. parameter min. max. unit f c f scl clock frequency 0 1 mhz t chcl t high clock pulse width high 260 - ns t clch t low clock pulse width low 700 (1) 1. 600ns when -20c t +85c. characterized only, not tested in production. -ns t xh1xh2 t r input signal rise time (2) 2. there is no min. or max. values for the input signal rise and fall times. however, it is recommended by the i2c specification that the input signal rise and fa ll times be more than 20 ns and less than 120 ns when f c < 1 mhz. (2) ns t xl1xl2 t f input signal fall time (2) (2) ns t ql1ql2 (3) 3. characterized only, not tested in production. t f sda (out) fall time 20 (4) 4. with cl = 10 pf. 120 ns t dxch t su:dat data in setup time 50 - ns t cldx t hd:dat data in hold time 0 - ns t clqx (5) 5. to avoid spurious start and stop conditions, a mini mum delay is placed between scl=1 and the falling or rising edge of sda. t dh data out hold time 50 - ns t clqv (6) 6. t clqv is the time (from the falling edge of scl) requi red by the sda bus line to reach either 0.3 v cc or 0.7 v cc , assuming that the rbus cbus time cons tant is within the values specified in figure 10 . t aa clock low to next data valid (access time) - 650 ns t chdl t su:sta start condition setup time 250 - ns t dlcl t hd:sta start condition hold time 250 - ns t chdh t su:sto stop condition setup time 250 - ns t dhdl t buf time between stop condition and next start condition 500 - ns t w t wr write time - 5 ms t ns (3) - pulse width ignored (input filter on scl and sda) -50ns
dc and ac parameters m24c64s-fcu 26/35 docid025449 rev 7 figure 9. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 400 khz figure 10. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at 1 mhz ,e&exv pdvwhu 0[[[ 5 exv 6&/ 5 exv [& exv qv +huh5 exv [& exv qv s) 06y9 n %xvolqh3xooxsuhvlvwrun? %xvolqhfdsdflwrus) 7kh5 exv [& exv wlph frqvwdqwpxvwehehorz wkhqvwlphfrqvwdqw olqhuhsuhvhqwhgrqwkhohiw & exv 9 && 6'$ 06y9 0[[[ 5 exv 9 && & exv 6&/ 6'$ 5exv6'$olqh3xooxsuhvlvwrun? 7khpd[lpxpydoxhriwkh wlphfrqvwdqw5 exv [& exv qvzkhq9 && ?9 qvzkhq9 && ?9 &exv6'$olqhsdudvlwlffdsdflwrus) 5exv&exvydoxhviruif 0+] , &exv pdvwhu
docid025449 rev 7 27/35 m24c64s-fcu dc and ac parameters 34 figure 11. ac waveforms ^> ^k? ^> ^/v ?o] ?>ys ?>yy ?,, ^?}? }v]?]}v ?,> ^??? }v]?]}v t?]??o ?t /??i ?o] ?y>y>? ^/v ?,> ^??? }v]?]}v ?y, ?>y ^ /v?? ^ zvp ?,, ?,> ^?}? }v]?]}v ^??? }v]?]}v ?y,y,? ^> ?,> ?>> ?>, ?y,y,? ?y>y>? ?y>y>? ?,>
package information m24c64s-fcu 28/35 docid025449 rev 7 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. 9.1 ultra thin wlcsp package information figure 12. ultra thin wlcsp- 4-bump, 0. 833 x 0.833 mm, wafer level chip scale package outline 1. drawing is not to scale. $=b0(b9 :dihuedfnvlgh 6lghylhz 2ulhqwdwlrq uhihuhqfh ; ddd ( ' ; < 'hwdlo$ eee = $ $ %xps $ = 'hwdlo$ 5rwdwhg? hhh = e; h ** ) h 6hdwlqjsodqh 2ulhqwdwlrq uhihuhqfh ; < t ggg0 = t fff0 = )
docid025449 rev 7 29/35 m24c64s-fcu package information 34 table 12. ultra thin wlcsp- 4-bump, 0. 833 x 0.833 mm, wafer level chip scale package mechanical data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. min typ max min typ max a 0.2400 0.2700 0.3000 0.0094 0.0106 0.0118 a1 -0.0950- -0.0037- a2 -0.1750- -0.0069- b (2) 2. dimension is measured at the maximum bum p diameter parallel to primary datum z -0.1850- -0.0073- d - 0.8330 0.8530 - 0.0328 0.0336 e - 0.8330 0.8530 - 0.0328 0.0336 e - 0.4000 - - 0.0157 - e1 -0.5000- -0.0197- f - 0.2170 - - 0.0085 - g 0.1670- -0.0066- aaa 0.1100 0.0043 bbb 0.1100 0.0043 ccc 0.1100 0.0043 ddd 0.0600 0.0024 eee 0.0600 0.0024
package information m24c64s-fcu 30/35 docid025449 rev 7 figure 13. ultra thin wlcsp- 4-bump, 0.833 x 0.833 mm, wafer level chip scale package outline with bsc 1. drawing is not to scale. 2. primary datum z and seating plane are defined by the spherical crowns of the bump. $=b37gb0(b9 :dihuedfnvlgh 6lghylhz 2ulhqwdwlrq uhihuhqfh ; ddd ( ' ; < 'hwdlo$ eee = $ $ %xps $ = 'hwdlo$ 5rwdwhg? hhh = e; h ** ) h 6hdwlqjsodqh 2ulhqwdwlrq uhihuhqfh ; < t ggg0 = t fff0 = ) %dfnvlghfrdwlqj wklfnqhvvpp $
docid025449 rev 7 31/35 m24c64s-fcu package information 34 figure 14. thin wlcsp- 4-bump, 0.833 x 0.833 mm, wafer level chip scale package recommended footprint table 13. ultra thin wlcsp- 4-bump, 0. 833 x 0.833 mm, wafer level chip scale package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.265 0.295 0.330 0.0104 0.0116 0.0130 a1 - 0.095 - - 0.0037 - a2 - 0.200 - - 0.0079 - a3 (bsc) - 0.025 - - 0.0010 - b (2) (3) 2. dimension is measured at the maximum bum p diameter parallel to primary datum z. 3. primary datum z and seating plane are defi ned by the spherical crowns of the bump. - 0.185 - - 0.0073 - d - 0.833 0.853 - 0.0328 0.0336 e - 0.833 0.853 - 0.0328 0.0336 e - 0.400 - - 0.0157 - e1 - 0.500 - - 0.0197 - f - 0.217 - - 0.0085 - g - 0.167 - - 0.0066 - aaa - - 0.110 - - 0.0043 bbb - - 0.110 - - 0.0043 ccc - - 0.110 - - 0.0043 ddd - - 0.060 - - 0.0024 eee - - 0.060 - - 0.0024 $=b)3b9 h h expsv[ ? pp
part numbering m24c64s-fcu 32/35 docid025449 rev 7 10 part numbering table 14. ordering information scheme example: m24 c64s -f cu 6 t /t f device type m24 = i 2 c serial access eeprom device function c64s = 64 kbits (8 k x 8 bits) operating voltage f = v cc = 1.7 v to 5.5 v package (1) 1. the package is ecopack2? (rohs compliant and free of brominated, chlorinated and antimony oxide flame retardants). cu = ultra-thin 4-bump wlcsp device grade 6 = device tested with standard test flow over ?40 to 85 c packing t = tape and reel packing process technology (2) 2. the process letter appears on the device package (m arking) and on the shipment box. please contact your nearest st sales office for further information. /t = process letter option blank = no back side coating (wlcsp height = 0.300mm) f = back side coating (wlcsp height = 0.330mm)
docid025449 rev 7 33/35 m24c64s-fcu part numbering 34 engineering samples parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st char ge. in no event, st wi ll be liable for any customer usage of these engineering samples in production. st quality has to be contacted prior to any decision to use these engineering samples to run qualification activity.
revision history m24c64s-fcu 34/35 docid025449 rev 7 11 revision history table 15. document revision history date revision changes 06-dec-2013 1 initial release. 21-mar-2014 2 updated supply voltage and operating temperature ranges in features updated section 1: description updated table 8: operating conditions 30-may-2014 3 added figure 12: ultra thin wlcsp- 4-bump, 0.833 x 0.833 mm, wafer level chip scale package outline . 04-dec-2014 4 updated features updated table 8: operating conditions added figure 10: maximum rbus value versus bus parasitic capacitance (cbus) for an i2c bus at 1 mhz added figure 12: ultra thin wlcsp- 4-bump, 0.833 x 0.833 mm, wafer level chip scale package outline added figure 13: ultra thin wlcsp- 4-bump, 0.833 x 0.833 mm, wafer level chip scale pack age outline with bsc added figure 14: thin wlcsp- 4-bump, 0.833 x 0.833 mm, wafer level chip scale package recommended footprint added table 11: 1 mhz ac characteristics . updated table 12: ultra thin wlcsp- 4-bump, 0.833 x 0.833 mm, wafer level chip scale package mechanical data added table 13: ultra thin wlcsp- 4-bump, 0.833 x 0.833 mm, wafer level chip scale package mechanical data added option f inside table 14: ordering information scheme 28-apr-2015 5 change from preliminary to production data status updated icc(read) value in table 9: dc characteristics updated figure 10: maximum rbus value versus bus parasitic capacitance (cbus) for an i2c bus at 1 mhz 26-aug-2015 6 updated: ? data retention and write cycles on cover page. ? figure 2 ? table 7 14-oct-2015 7 added: ? note 1 on table 11 . ? notes 1 and 2 on table 14
docid025449 rev 7 35/35 m24c64s-fcu 35 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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